Pc-concepts SHG2 DP Manuel d'utilisateur télécharger pdf (Page 38)

Baseboard PCI I/O Subsystem Intel® SHG2 DP Server Board Technical Product Specification

Intel Order Number C11343-001 Revision 1.0

The XIOAPIC logic inside CSB5 has 48 entries of which 16 entries are for legacy interrupts 0-

15, and 32 entries are for PCI interrupts. The 48 entries are implemented as three 16-entry

XIOAPIC units. The basic building block for the XIOAPIC is a 16-entry IOAPIC.

The SHG2 baseboard supports mapping (redirection) of any of the 32 PCI interrupt sources to

legacy interrupts. The legacy interrupt lines after mapping logic is connected to the input of

82559 inside of CSB5.

3.6.1 Serialized IRQ support

The SHG2 baseboard supports the serialized interrupt delivery mechanism. The serialized IRQ

(SERIRQ) consists of a start frame, a minimum of 17 interrupt request (IRQ)/ data channels,

and a stop frame. Any slave device in quiet mode may initiate the start frame. While in the

continuous mode, the start frame is initiated by the host controller.

3.6.2 IRQ scan for PCIIRQ

The IRQ/data frame structure within the CSB5 includes the ability to handle up to 32 sampling

channels with the standard implementation. The SHG2 baseboard has a total of 16 PCIIRQs

that are connected through an external PCI interrupt serializer for PCIIRQ scan mechanism,

which then serializes the PCIIRQ orders into the CSB5 IRQ/data frame structure.

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Pc-concepts SHG2 DP Manuel d'utilisateur Page 38